The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2019
Filed:
May. 22, 2017
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Dexter Tamio Chun, San Diego, CA (US);
Richard Alan Stewart, San Diego, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/08 (2006.01); G06F 3/06 (2006.01); G06F 1/3234 (2019.01); G06F 1/324 (2019.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); G06F 1/324 (2013.01); G06F 1/3275 (2013.01); G06F 3/0611 (2013.01); G06F 3/0629 (2013.01); G06F 3/0683 (2013.01); G06F 13/1689 (2013.01);
Abstract
Pipelined logic latency in a memory system operating at a reduced frequency may be compensated for. Pipelined logic may be controlled using at least first and second clock signals. All registers of the pipelined logic may be controlled using the first clock signal when the memory system is operating at a higher frequency. However, when the memory system is operating at a reduced frequency, one or more registers may be controlled using the first clock signal, and one or more other registers may be controlled using the second clock signal.