The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Jun. 21, 2016
Applicant:

Abb Schweiz Ag, Baden, CH;

Inventor:

Robert Joseph Roessler, Wylie, TX (US);

Assignee:

ABB SCHWEIZ AG, Baden, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01K 3/10 (2006.01); H05K 1/18 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 3/00 (2006.01); H05K 3/30 (2006.01); H05K 3/42 (2006.01);
U.S. Cl.
CPC ...
H05K 1/181 (2013.01); H05K 1/0265 (2013.01); H05K 1/0298 (2013.01); H05K 1/113 (2013.01); H05K 1/115 (2013.01); H05K 3/0047 (2013.01); H05K 3/303 (2013.01); H05K 3/424 (2013.01); H05K 3/429 (2013.01); H05K 2201/098 (2013.01); H05K 2201/1003 (2013.01); H05K 2201/10166 (2013.01); H05K 2203/1476 (2013.01); Y10T 29/49165 (2015.01);
Abstract

A method of manufacturing a printed circuit board includes providing a printed circuit board (PCB) substrate including at least one insulating layer and first and second conductive layers separated from one another by the at least one insulating layer, forming a first via hole in the PCB substrate extending from the first conductive layer to the second conductive layer, where the first via hole is defined by a first sidewall of the PCB substrate, forming a second via hole in the PCB substrate, where the second via hole is defined by a second sidewall of the PCB substrate, and selectively plating the first sidewall and the second sidewall to form a first via and a second via, respectively, where the first via and the second via have different via sidewall thicknesses.


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