Multiplexed sigma-delta analog-to-digital converter

Abstract

A sigma-delta ADC circuit with an analog loop filter circuit can be multiplexed between different inputs by flushing the memory of the analog loop filter integrators and the digital decimation filter and filling it with new data for the current input. However, filling the memory can be slow with respect to the sampling frequency because the information about past history has to be built up before meaningful output data can be generated. Thus, the multiplexing rate between channels using a sigma-delta ADC circuit can be slowed by such memory flushing. A multiplexed sigma-delta ADC circuit is described that can overcome these problems so as to be able to support cycle-by-cycle sampling of multiple channels. These techniques can provide a fast sigma-delta analog-to-digital converter (ADC) circuit that is small in area and that can multiplex over a number of channels dynamically.