The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Sep. 18, 2017
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventor:

Roh Yamamoto, Kanagawa, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 1/00 (2006.01); H03K 3/00 (2006.01); H03K 3/356 (2006.01); G09G 3/20 (2006.01); G09G 3/36 (2006.01); G11C 11/412 (2006.01); H03K 3/012 (2006.01); H03K 19/00 (2006.01); G11C 19/28 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356017 (2013.01); G09G 3/20 (2013.01); G09G 3/3611 (2013.01); G11C 11/412 (2013.01); G11C 19/28 (2013.01); H03K 3/012 (2013.01); H03K 3/356139 (2013.01); H03K 19/0013 (2013.01); H03K 19/018521 (2013.01);
Abstract

An object is to provide a level shift circuit that operates stably. A semiconductor device includes a level shift circuit including first to fourth transistors and a buffer circuit. One of a source and a drain (S/D) of the first transistor is connected to one of a source and a drain of the second transistor. The other of the source and the drain of the second transistor is connected to one of a source and a drain of the third transistor. A gate of the first transistor and a gate of the fourth transistor are connected to the other of the source and the drain of the second transistor and the one of the source and the drain of the third transistor. A gate of the third transistor is connected to a wiring to which an input signal is input. An input terminal of the buffer circuit is connected to one of a source and a drain of the fourth transistor. An output terminal of the buffer circuit is connected to a gate of the second transistor and a wiring to which an output signal is output.


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