The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Jun. 28, 2018
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Gyu Wan Kwon, San Jose, CA (US);

Jae Hyeong Kim, San Ramon, CA (US);

Amal Akbar, San Jose, CA (US);

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/16 (2006.01); H03K 3/012 (2006.01); H03K 17/08 (2006.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); H03K 17/08 (2013.01);
Abstract

A semiconductor device includes: a power-gated logic circuit suitable for operating in response to a first power gating enable signal which is deactivated in a standby mode and activated in an active mode; a transmission unit suitable for selectively transmitting an output signal of the power-gated logic circuit to an output terminal in response to a third power gating enable signal; a clocked latch unit suitable for latching a signal of the output terminal in the standby mode and an initial stage of the active mode in response to a second power gating enable signal; and an internal circuit suitable for operating based on the signal of the output terminal, wherein the first to third power gating enable signals are sequentially activated.


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