The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Jan. 18, 2017
Applicant:

Sumitomo Electric Industries, Ltd., Osaka, JP;

Inventor:

Hirotaka Oomori, Osaka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 7/48 (2007.01); H02M 7/537 (2006.01); H01L 25/07 (2006.01); H01L 25/18 (2006.01); H02M 1/34 (2007.01); H02M 1/32 (2007.01); H02M 7/00 (2006.01); H02M 7/5387 (2007.01);
U.S. Cl.
CPC ...
H02M 7/537 (2013.01); H01L 25/07 (2013.01); H01L 25/18 (2013.01); H02M 1/32 (2013.01); H02M 1/34 (2013.01); H02M 7/003 (2013.01); H02M 7/48 (2013.01); H02M 7/5387 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/49113 (2013.01); H02M 2001/348 (2013.01);
Abstract

A semiconductor module according to an embodiment includes an insulating substrate having a power conversion circuit mounted thereon, a first transistor constituting an upper arm, a second transistor constituting a lower arm, a first input interconnection pattern coupled to a positive-side input terminal, a second input interconnection pattern coupled to a negative-side input terminal, an output interconnection pattern coupled to an output terminal, and an absorbing device configured to absorb surge voltage, wherein the first input interconnection pattern includes a first-transistor mounting area on which the first transistor is mounted, wherein the output interconnection pattern includes a second-transistor mounting area on which the second transistor is mounted, wherein the second input interconnection pattern includes an absorbing-device connecting area disposed between the first and second transistor mounting areas, and wherein the absorbing-device connecting area is electrically coupled to the first-transistor mounting area through the absorbing device.


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