The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Apr. 04, 2018
Applicant:

Shanghai Huali Microelectronics Corporation, Shanghai, CN;

Inventor:

Xiaoliang Tang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/792 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); H01L 21/28282 (2013.01); H01L 29/42344 (2013.01); H01L 29/66833 (2013.01);
Abstract

The present disclosure provides a manufacturing method for a transistor with an SONOS structure, including providing a semiconductor substrate, wherein the semiconductor substrate includes a select transistor well and a memory transistor well; depositing an oxide layer on an upper surface of the select transistor well, depositing an ONO memory layer on an upper surface of the memory transistor well, depositing a barrier wall over adjacent portions of the select transistor well and the memory transistor well, depositing polycrystalline silicon covering the oxide layer, the ONO memory layer, and the barrier wall, and etching the polycrystalline silicon, to retain the polycrystalline silicon deposited on both sides of the barrier wall so as to form a select gate and a memory gate, and removing the oxide layer and the ONO layer on a surface of the semiconductor substrate other than the select gate, the barrier wall, and the memory gate.


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