The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Jun. 22, 2017
Applicant:

Wuhan China Star Optoelectronics Technology Co., Ltd., Wuhan, Hubei, CN;

Inventor:

Tao Wang, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 21/266 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/167 (2006.01); H01L 21/285 (2006.01); H01L 21/3213 (2006.01); G02F 1/1343 (2006.01); H01L 21/027 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G02F 1/1333 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78633 (2013.01); G02F 1/1368 (2013.01); G02F 1/13439 (2013.01); G02F 1/136209 (2013.01); H01L 21/0274 (2013.01); H01L 21/02271 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/266 (2013.01); H01L 21/2855 (2013.01); H01L 21/32139 (2013.01); H01L 27/1222 (2013.01); H01L 27/1248 (2013.01); H01L 27/1262 (2013.01); H01L 27/1288 (2013.01); H01L 29/167 (2013.01); H01L 29/66757 (2013.01); H01L 29/78675 (2013.01); G02F 1/133345 (2013.01); G02F 2001/13685 (2013.01); G02F 2001/133357 (2013.01); G02F 2202/104 (2013.01);
Abstract

A low temperature polysilicon (LTPS) thin film transistor (TFT) substrate and a method for manufacturing the same are provided. The method includes: sequentially forming a plurality of light-shielding portions, a buffer layer, and a plurality of island-shaped polysilicon portions on a substrate; performing light ion doping over two sides of the island-shaped polysilicon portions to form doped regions and channel regions; sequentially forming a gate insulating layer and a plurality of gate electrodes; performing heavy ion doping over the doped region that are not covered by the gate electrodes to form N-type heavily doped regions and N-type lightly doped regions; and forming an interlayer insulating layer as well as a source electrode and a drain electrode which are electrically connected to the N-type heavily doped regions on the gate electrodes.


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