The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Dec. 29, 2017
Applicant:

Fairchild Semiconductor Corporation, Sunnyvale, CA (US);

Inventor:

Andrei Konstantinov, Sollentuna, SE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/04 (2006.01); H01L 29/10 (2006.01); H01L 29/167 (2006.01); H01L 29/808 (2006.01); H01L 29/417 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7803 (2013.01); H01L 21/046 (2013.01); H01L 21/047 (2013.01); H01L 21/049 (2013.01); H01L 21/0455 (2013.01); H01L 21/0465 (2013.01); H01L 29/0611 (2013.01); H01L 29/0638 (2013.01); H01L 29/1037 (2013.01); H01L 29/1041 (2013.01); H01L 29/1095 (2013.01); H01L 29/167 (2013.01); H01L 29/1608 (2013.01); H01L 29/4236 (2013.01); H01L 29/42368 (2013.01); H01L 29/66068 (2013.01); H01L 29/7813 (2013.01); H01L 29/7832 (2013.01); H01L 29/0878 (2013.01); H01L 29/41766 (2013.01); H01L 29/8083 (2013.01);
Abstract

In a general aspect, an apparatus can include a semiconductor substrate, a drift region disposed in the semiconductor substrate; a body region disposed in the drift region and a source region disposed in the body region. The apparatus can also include a gate trench disposed in the semiconductor substrate. The apparatus can further include a gate dielectric disposed on a sidewall and a bottom surface of the gate trench, the gate dielectric on the sidewall defining a first interface with the body region and the gate dielectric on the bottom surface defining a second interface with the body region. The apparatus can still further include a gate electrode disposed on the gate dielectric and a lateral channel region disposed in the body region, the lateral channel region being defined along the second interface.


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