The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Jul. 25, 2016
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Jian Min, Beijing, CN;

Xiaolong Li, Beijing, CN;

Tao Gao, Beijing, CN;

Liangjian Li, Beijing, CN;

Zhengyin Xu, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/30 (2006.01); H01L 27/12 (2006.01); H01L 29/36 (2006.01); H01L 29/66 (2006.01); H01L 21/027 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66757 (2013.01); H01L 21/0262 (2013.01); H01L 21/0272 (2013.01); H01L 21/0274 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02675 (2013.01); H01L 21/3003 (2013.01); H01L 27/1285 (2013.01); H01L 27/1288 (2013.01); H01L 29/36 (2013.01); H01L 29/78618 (2013.01); H01L 29/78675 (2013.01);
Abstract

The present application discloses a method of fabricating a polycrystalline silicon thin film transistor, the method including forming an amorphous silicon layer on a base substrate having a pattern corresponding to a polycrystalline silicon active layer of the thin film transistor; the amorphous silicon layer having a first region corresponding to a source electrode and drain electrode contact region in the polycrystalline silicon active layer and a second region corresponding to a channel region in the polycrystalline silicon active layer; forming a first dopant layer on a side of the second region distal to the base substrate; forming a second dopant layer on a side of the first region distal to the base substrate; and crystallizing the amorphous silicon layer, the first dopant layer, and the second dopant layer to form the polycrystalline silicon active layer, the polycrystalline silicon active layer being doped with a dopant of the first dopant layer in the second region and doped with a dopant of the second dopant layer in the first region during the step of crystallizing the amorphous silicon layer.


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