The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Apr. 10, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Young-suk Lee, Daejeon, KR;

Tae-hee Lee, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11578 (2017.01); H01L 27/11582 (2017.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/11519 (2017.01); H01L 27/1157 (2017.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/562 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01);
Abstract

A semiconductor device including: a substrate including a top surface configured to extend in a first direction and a second direction that are perpendicular to each other; gate stack structures disposed on the substrate, spaced apart from one another in the first direction and configured to extend in the second direction; a first region in which levels of top surfaces of the gate stack structures are constant; a second region in which levels of top surfaces of the gate stack structures are stepped, the second region configured to surround at least a portion of the first region; and conductive lines disposed in the second region between the gate stack structures and configured to extend in the second direction in an uneven form.


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