The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Feb. 21, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Won-Gi Chang, Hwaseong-si, KR;

Dongwon Lee, Anyang-si, KR;

Myung-Sung Kang, Yongin-si, KR;

Hyein Yoo, Pyeongtaek-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 25/00 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 24/83 (2013.01); H01L 25/0657 (2013.01); H01L 2224/83201 (2013.01); H01L 2224/83931 (2013.01); H01L 2224/83947 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes stacking, on a package substrate, first semiconductor chips. Each of the first semiconductor chips includes a first adhesive film. The method includes stacking, respectively on the first semiconductor chips, second semiconductor chips. Each of the second semiconductor chips includes a second adhesive film. The method includes compressing the first and second adhesive films to form an adhesive structure. The adhesive structure includes an extension disposed on sidewalls of the first and second semiconductor chips. The method includes removing the extension. The method includes forming a first molding layer substantially covering the first and second semiconductor chips. The method includes performing a cutting process on the package substrate between the first and second semiconductor chips to form a plurality of semiconductor packages each including at least one of the first semiconductor chips and at least one of the second semiconductor chips.


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