The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Oct. 19, 2017
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Dmitri Alex Tschumakow, Dresden, DE;

Claus Dahl, Dresden, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 23/522 (2006.01); H01L 29/08 (2006.01); H01L 29/737 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 23/5226 (2013.01); H01L 29/0653 (2013.01); H01L 29/0817 (2013.01); H01L 29/1004 (2013.01); H01L 29/66242 (2013.01); H01L 29/7371 (2013.01);
Abstract

A method for manufacturing includes providing a semiconductor substrate having a semiconductor device including at least two device layers to be contacted. A first device layer is smaller than a lithographic minimum feature size used for manufacturing the semiconductor device. Further, the method includes providing an isolation layer on the semiconductor device such that the semiconductor device is covered by the isolation layer; planarizing the isolation layer up to the semiconductor device; providing a first lithographic mask on the semiconductor device, such that the first device layer and a portion of the isolation layer are covered by the first lithographic mask; selectively removing the isolation layer to expose a second device layer while maintaining the portion of the isolation layer that is covered by the first lithographic mask; and providing a stop layer on the first device layer, the second device layer and the portion of the isolation layer.


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