The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Nov. 27, 2017
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventor:

Makoto Suwada, Kawasaki, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 11/406 (2006.01); H01L 25/065 (2006.01); G11C 5/04 (2006.01); G11C 7/04 (2006.01); H01L 23/00 (2006.01); G11C 8/12 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40626 (2013.01); G11C 5/04 (2013.01); G11C 7/04 (2013.01); G11C 11/40618 (2013.01); H01L 25/0657 (2013.01); G11C 8/12 (2013.01); H01L 24/16 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16227 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06582 (2013.01); H01L 2225/06589 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/1436 (2013.01);
Abstract

A semiconductor device in which a plurality of chips each including a memory circuit is stacked, the semiconductor device includes a transmission path including a plurality of microbumps formed in the plurality of chips, measurement circuitry that detects a reflected waveform when a signal is transmitted in the transmission path and measures propagation delay time for a certain part on the transmission path from the reflected waveform that has been detected, determination circuitry that calculates temperature of each memory area that corresponds to the certain part from the propagation delay time that has been measured by the measurement circuitry, and control circuitry that sets a refresh interval of each memory area, based on the temperature of each memory area, which has been calculated by the determination circuitry, and executes a refresh operation of the memory circuit in each memory area at the refresh interval that has been set.


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