The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Jun. 10, 2015
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Abdulkadir U. Diril, Mountain View, CA (US);

Adam T. Moerschell, San Jose, CA (US);

Anthony P. DeLaurier, Los Altos, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06T 15/04 (2011.01); G06T 1/20 (2006.01); G09G 5/39 (2006.01);
U.S. Cl.
CPC ...
G06T 15/04 (2013.01); G06T 1/20 (2013.01); G09G 5/39 (2013.01); G06T 2200/28 (2013.01); G06T 2210/36 (2013.01);
Abstract

Techniques are disclosed relating to determining the location of a specified level of detail for a graphics texture. In some embodiments, an apparatus includes texture processing circuitry configured to receive information specifying a particular mipmap in a chain of stored mipmaps for a graphics texture and determine an offset address for the particular mipmap. In these embodiments, the texture processing circuitry is configured to determine the offset address by operating on a value that indicates a greatest potential chain size for chains of mipmaps in a graphics processing element. In these embodiments, the operating includes masking upper bits of the value based on a size of the texture and masking lower bits of the value based on a position of the specified mipmap in the chain of stored mipmaps. Disclosed techniques may reduce power consumption and/or area of circuitry configured to determine the offset.


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