The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Feb. 24, 2017
Applicant:

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Inventors:

Ibrahima Diop, Marseilles, FR;

Pierre-Yvan Liardet, Peynier, FR;

Yanis Linge, Fuveau, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/52 (2013.01); G06F 7/523 (2006.01); G06F 7/72 (2006.01);
U.S. Cl.
CPC ...
G06F 21/52 (2013.01); G06F 7/523 (2013.01); G06F 7/72 (2013.01); G06F 7/723 (2013.01); G06F 2207/7242 (2013.01); G06F 2221/032 (2013.01);
Abstract

A method of protecting a modular calculation on a first number and a second number, executed by an electronic circuit, including the steps of: combining the second number with a third number to obtain a fourth number; executing the modular calculation on the first and fourth numbers, the result being contained in a first register or memory location; initializing a second register or memory location to the value of the first register or to one; and successively, for each bit at state 1 of the third number: if the corresponding bit of the fourth number is at state 1, multiplying the content of the second register or memory location by the inverse of the first number and placing the result in the first register or memory location, if the corresponding bit of the fourth number is at state 0, multiplying the content of the second register or memory location by the first number and placing the result in the first register or memory location.


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