The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Mar. 07, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Gregory W. Alexander, Pflugerville, TX (US);

Brian D. Barrick, Pflugerville, TX (US);

Thomas W. Fox, Hopewell Junction, NY (US);

Christian Jacobi, West Park, NY (US);

Anthony Saporito, Highland, NY (US);

Somin Song, Austin, TX (US);

Aaron Tsai, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0811 (2016.01); G06F 12/0813 (2016.01); G06F 12/0804 (2016.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 12/0804 (2013.01); G06F 12/0813 (2013.01); G06F 12/0875 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01); G06F 2212/62 (2013.01);
Abstract

A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.


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