The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 2019
Filed:
Mar. 03, 2017
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Harmander Singh, Cedar Park, TX (US);
Sebastien Weyland, Austin, TX (US);
Suresh Kumar Venkumahanti, Austin, TX (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G11C 5/14 (2006.01); G11C 16/20 (2006.01); G11C 16/30 (2006.01); G11C 29/02 (2006.01);
U.S. Cl.
CPC ...
G06F 1/26 (2013.01); G11C 5/148 (2013.01); G11C 16/20 (2013.01); G11C 16/30 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01);
Abstract
A programmable logic circuit such as a finite state machine is provided that is configured to determine a memory array power-up sequence from a configuration signal to successively enable each memory array. A delay circuit triggers an initial memory bank in each enabled memory array to power-up without a delay. The delay circuit then counts responsive to a clock to determine a delay between a successive triggering of remaining memory banks in each enabled memory array to power-up.