The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Jul. 03, 2018
Applicants:

University of Electronic Science and Technology of China, Chengdu, CN;

Institute of Electronic and Information Engineering of Uestc IN Guangdong, Dongguan, CN;

Inventors:

Xin Ming, Chengdu, CN;

Jiahao Zhang, Chengdu, CN;

Wenlin Zhang, Chengdu, CN;

Di Gao, Chengdu, CN;

Xuan Zhang, Chengdu, CN;

Zhuo Wang, Chengdu, CN;

Bo Zhang, Chengdu, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/575 (2006.01); H03F 3/30 (2006.01); H03F 3/45 (2006.01); H03F 3/08 (2006.01);
U.S. Cl.
CPC ...
G05F 1/575 (2013.01); H03F 3/082 (2013.01); H03F 3/3061 (2013.01); H03F 3/45183 (2013.01); H03F 3/45264 (2013.01); H03F 3/45269 (2013.01); H03F 3/45273 (2013.01);
Abstract

A ripple pre-amplification based fully integrated LDO pertains to the technical field of power management. The positive input terminal of a transconductance amplifier is connected to a reference voltage Vref, and the negative input terminal of the transconductance amplifier is connected to the feedback voltage V. The output terminal of the transconductance amplifier is connected to the negative input terminal of a transimpedance amplifier and the negative input terminal of an error amplifier. The positive input terminal of the transimpedance amplifier is connected to the ground GND, and the output terminal of the transimpedance amplifier is connected to the positive input terminal of the error amplifier. The gate terminal of the power transistor Mis connected to the output terminal of the error amplifier, the source terminal of the power transistor Mis connected to an input voltage V, and the drain terminal of the power transistor Mis grounded.


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