The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Oct. 17, 2017
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventors:

Stephen Bowling, Chandler, AZ (US);

Igor Wojewoda, Tempe, AZ (US);

Dereck Fernandes, Chandler, AZ (US);

Manivannan Balu, Bangalore, IN;

Yong Yuenyongsgool, Gilbert, AZ (US);

Timothy Phoenix, Pepperell, MA (US);

Steve Bradley, Phoenix, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G01R 31/3177 (2006.01); G06F 15/80 (2006.01); G11C 29/14 (2006.01); G11C 29/26 (2006.01); G11C 29/48 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31724 (2013.01); G01R 31/3177 (2013.01); G01R 31/31723 (2013.01); G06F 15/8061 (2013.01); G11C 29/14 (2013.01); G11C 29/26 (2013.01); G11C 29/48 (2013.01); G11C 2029/0401 (2013.01); G11C 2029/0409 (2013.01);
Abstract

In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.


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