The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2019
Filed:
Jun. 29, 2015
Applicant:
Hewlett-packard Development Company, L.p., Houston, TX (US);
Inventors:
Charles Nathan Logan, Boise, ID (US);
Adrian Rothenbuhler, Boise, ID (US);
Christine M. Wells, Boise, ID (US);
Assignee:
Hewlett-Packard Development Company, L.P., Spring, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 3/40 (2006.01); H05K 1/02 (2006.01); H05K 1/09 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0275 (2013.01); H05K 1/09 (2013.01); H05K 1/111 (2013.01); H05K 1/112 (2013.01); H05K 3/4007 (2013.01); H05K 3/4038 (2013.01); H05K 1/0298 (2013.01); H05K 2201/094 (2013.01); H05K 2201/09227 (2013.01); H05K 2201/09409 (2013.01); H05K 2201/09781 (2013.01);
Abstract
In one implementation, a printed circuit board (PCB) includes a plurality of pads that form a pad pattern on the PCB. In that implementation, the plurality of pads include a group of load pads, a dummy pad, and a false pad. The group of load pads act as contact points to establish an electrical path between a first circuitry and a second circuitry. The dummy pad is coupled to a via that floats electrically and the false pad is coupled to a third circuitry.