The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Sep. 30, 2015
Applicant:

Emc Corporation, Hopkinton, MA (US);

Inventor:

John Gemignani, Jr., Bremerton, WA (US);

Assignee:

EMC IP HOLDING COMPANY LLC, Hopkinton, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/177 (2006.01); H04L 29/06 (2006.01); H04L 29/08 (2006.01);
U.S. Cl.
CPC ...
H04L 69/162 (2013.01); H04L 67/34 (2013.01);
Abstract

An enhanced address domain is presented herein. A system can comprise a processor; and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising: creating an upper-layer socket of an enhanced address domain; allocating a protocol control block (PCB) and associating the PCB with the upper-layer socket—the PCB storing information representing a private state of the upper-layer socket; creating a lower-layer socket of an existing address domain—the lower-layer socket referenced from the upper-layer socket using the PCB; and installing upcall(s) on the lower-layer socket to be intercepted via the enhanced address domain. In an aspect, the upper-layer socket supports enhancement(s) to the existing address domain and a socket type of the lower-layer socket.


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