The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Jul. 12, 2017
Applicant:

Delta Electronics, Inc., Taoyuan, TW;

Inventors:

Chao-Feng Cai, Taoyuan, TW;

Jian-Hong Zeng, Taoyuan, TW;

Zeng Li, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 23/50 (2006.01); H01L 23/00 (2006.01); H01L 29/40 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7826 (2013.01); H01L 23/50 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 29/7816 (2013.01); H01L 29/1083 (2013.01); H01L 29/402 (2013.01); H01L 29/41766 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/18 (2013.01); H01L 2924/19104 (2013.01);
Abstract

A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.


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