The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Jan. 05, 2018
Applicant:

Fuji Electric Co., Ltd., Kanagawa, JP;

Inventors:

Keishirou Kumada, Nagano, JP;

Yuichi Hashizume, Nagano, JP;

Yasuyuki Hoshi, Nagano, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/22 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/167 (2006.01); H01L 29/36 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66068 (2013.01); H01L 21/02529 (2013.01); H01L 21/02636 (2013.01); H01L 21/221 (2013.01); H01L 29/0688 (2013.01); H01L 29/167 (2013.01); H01L 29/1608 (2013.01); H01L 29/36 (2013.01); H01L 29/41741 (2013.01); H01L 29/4236 (2013.01); H01L 29/42356 (2013.01); H01L 29/66333 (2013.01); H01L 29/66348 (2013.01); H01L 29/66712 (2013.01); H01L 29/66734 (2013.01); H01L 29/7395 (2013.01); H01L 29/7397 (2013.01); H01L 29/7813 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate insulating film, and a gate electrode. The semiconductor device further includes, in a region of the first semiconductor layer across or adjacent to a p-n junction therein that does not overlap the second semiconductor region in a plan view except lateral edges thereof, a lifetime killer region having lifetime killers implanted therein.


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