The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2019
Filed:
Mar. 15, 2018
Applicant:
Microchip Technology Incorporated, Chandler, AZ (US);
Inventors:
Assignee:
MICROCHIP TECHNOLOGY INCORPORATED, Chandler, AZ (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 29/423 (2006.01); H01L 27/11521 (2017.01); G11C 16/08 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42328 (2013.01); H01L 27/11521 (2013.01); G11C 16/0408 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); H01L 29/7841 (2013.01);
Abstract
A memory cell, e.g., a flash memory cell, includes a substrate, a floating gate formed over the substrate, and a word line and an erase gate formed over the floating gate. The word line overlaps the floating gate by a first lateral overlap distance, and the erase gate overlaps the floating gate by a second lateral overlap distance that is substantially greater than the first lateral distance. This configuration allows the program and erase coupling to the floating gate to be optimized independently, e.g., to decrease or minimize the program current and/or increase or maximize the erase current for the cell.