The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Feb. 26, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Shingo Nakazawa, Kanagawa, JP;

Tsuneo Inaba, Kanagawa, JP;

Hiroyuki Takenaka, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/22 (2006.01); H01L 27/24 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/222 (2013.01); G11C 13/0004 (2013.01); H01L 27/2481 (2013.01); G11C 2213/71 (2013.01); G11C 2213/81 (2013.01);
Abstract

A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. One of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.


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