The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

May. 08, 2017
Applicant:

Canon Kabushiki Kaisha, Tokyo, JP;

Inventors:

Taro Kato, Tokyo, JP;

Fumihiro Inui, Yokohama, JP;

Takehiko Soda, Yokohama, JP;

Akira Okita, Yamato, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 7/34 (2006.01); H04N 5/232 (2006.01); H04N 5/359 (2011.01); H04N 5/378 (2011.01); H01L 27/146 (2006.01); H04N 5/3745 (2011.01);
U.S. Cl.
CPC ...
H01L 27/1463 (2013.01); G02B 7/34 (2013.01); H01L 27/14612 (2013.01); H01L 27/14627 (2013.01); H01L 27/14643 (2013.01); H04N 5/23212 (2013.01); H04N 5/359 (2013.01); H04N 5/378 (2013.01); H04N 5/37457 (2013.01);
Abstract

An imaging device includes a plurality of pixels two-dimensionally disposed. At least part of the plurality of pixels includes a first photoelectric conversion unit and a second photoelectric conversion unit provided in a semiconductor substrate and each including a first semiconductor region of a first conductivity type for accumulating a signal charge, a first isolation region provided in the semiconductor substrate between the first photoelectric conversion unit and the second photoelectric conversion unit and including a second semiconductor region forming a first potential barrier for the signal charge in the first semiconductor region, and a second isolation region provided in the semiconductor substrate between the first photoelectric conversion unit and the second photoelectric conversion units and including a trench isolation forming a second potential barrier higher than the first potential barrier for the signal charge in the first semiconductor region.


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