The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Aug. 08, 2016
Applicant:

Delta Electronics (Shanghai) Co., Ltd, Shanghai, CN;

Inventors:

Tao Wang, Shanghai, CN;

Zhenqing Zhao, Shanghai, CN;

Kai Lu, Shanghai, CN;

Zeng Li, Shanghai, CN;

Jianhong Zeng, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 21/54 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/07 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 21/54 (2013.01); H01L 23/3142 (2013.01); H01L 23/3178 (2013.01); H01L 24/03 (2013.01); H01L 24/08 (2013.01); H01L 24/49 (2013.01); H01L 25/072 (2013.01); H01L 2224/03009 (2013.01); H01L 2224/085 (2013.01); H01L 2224/0805 (2013.01); H01L 2224/73221 (2013.01);
Abstract

The embodiments of the present disclosure relate to a power package module of multiple power chips and a method of manufacturing a power chip unit. The power package module of multiple power chips includes: a power chip unit including at least two power chips placed in parallel and a bonding part bonding the two power chips; a substrate supporting the power chip unit and including a metal layer electronically connecting with the power chip unit; and a sealing layer isolating the power chip unit on the substrate from surroundings to seal the power chip unit; the bonding part and the sealing layer are made from different insulated material, the distance of a gap between the two power chips placed in parallel is smaller than or equal to a preset width, and the bonding part is filled in the gap, insulatedly bonding the two power chips placed in parallel.


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