The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Sep. 20, 2017
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Jeong-Hwan Kim, Gyeonggi-do, KR;

Jin-Ho Kim, Gyeonggi-do, KR;

Sang-Hyun Sung, Chungcheongbuk-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 11/408 (2006.01); G11C 8/14 (2006.01); G11C 8/08 (2006.01); G11C 8/10 (2006.01); G11C 16/04 (2006.01); H01L 27/11575 (2017.01); H01L 27/11582 (2017.01); G11C 5/02 (2006.01); G11C 7/18 (2006.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
G11C 11/4087 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); G11C 8/14 (2013.01); G11C 16/0441 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01); G11C 5/025 (2013.01); G11C 7/18 (2013.01); H01L 27/11565 (2013.01);
Abstract

A semiconductor memory device includes a memory cell array and a row decoder disposed in a first direction over a substrate and a plurality of coupling lines for electrically coupling the memory cell array and the row decoder. Each of the coupling lines includes a first conductive line disposed in the first direction; a second conductive line disposed parallel to the first conductive line; and a pad coupling the first conductive line and the second conductive line, and coupled to the memory cell array or the row decoder through a contact plug. The coupling lines are routed from both sides of the pad in the first direction.


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