The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Oct. 05, 2017
Applicant:

Gyrfalcon Technology Inc., Milpitas, CA (US);

Inventors:

Chyu-Jiuh Torng, Dublin, CA (US);

Lin Yang, Milpitas, CA (US);

Qi Dong, San Jose, CA (US);

Daniel H. Liu, San Jose, CA (US);

Assignee:

Gyrfalcon Technology Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/4078 (2006.01); G06F 15/18 (2006.01); G11C 11/02 (2006.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G11C 11/4078 (2013.01); G06F 15/18 (2013.01); G06N 20/00 (2019.01); G11C 11/02 (2013.01);
Abstract

An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.


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