The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Sep. 25, 2017
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Juseok Lee, Paju-si, KR;

HaeSeung Lee, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3258 (2016.01); G09G 3/20 (2006.01); G09G 3/3266 (2016.01); G09G 3/3291 (2016.01); G09G 3/3233 (2016.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3258 (2013.01); G09G 3/2096 (2013.01); G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); G09G 3/3291 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/063 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0295 (2013.01); G09G 2320/045 (2013.01); G09G 2320/0693 (2013.01); G09G 2330/021 (2013.01); G09G 2330/026 (2013.01); G09G 2330/028 (2013.01); H03K 19/21 (2013.01);
Abstract

A display panel driving unit can include: a timing controller to supply a power on reset signal for starting a sensing operation for pixel compensation during a sensing period before displaying an image; a power management integrated circuit (PMIC) to supply a high level reference voltage reset signal to the timing controller, and generate a control signal; and a control circuit to receive the high level reference voltage reset signal and the PMIC, in response to the high level reference voltage reset signal transitioning from a high to low logic level and then from the low logic level back to the high logic level, shift the power on reset signal to transition from a high to low logic level and then from the low logic level back to high, to follow the high level reference voltage reset signal, and supply the power on reset signal to the timing controller.


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