The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2019
Filed:
Mar. 25, 2016
International Business Machines Corporation, Armonk, NY (US);
Terence B. Hook, Jericho, VT (US);
Larry Wissel, Williston, VT (US);
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Abstract
Methods and systems for checking a wafer-level design for compliance with a rule include determining whether each chip layout out of multiple chip layouts complies internally with one or more layout design rules. A tile area is determined, having a size that is based on the one or more layout design rules, that crosses a boundary between adjacent chip layouts and that leaves at least a portion of each chip layout uncovered. It is determined whether portions of the plurality of chip layouts inside the tile area comply with the one or more layout design rules. The chip layouts are modified, if chip layout area within the tile area fails to comply with the design rule, to bring non-compliant periphery chip regions into compliance.