The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Jun. 28, 2017
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Matthew Hastings, Seattle, WA (US);

Torsten Karzig, Goleta, CA (US);

Parsa Bonderson, Santa Barbara, CA (US);

Michael Freedman, Santa Barbara, CA (US);

Roman Lutchyn, Santa Barbara, CA (US);

Chetan Nayak, Santa Barbara, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01N 7/02 (2006.01); G06F 15/80 (2006.01); G06N 10/00 (2019.01);
U.S. Cl.
CPC ...
G06F 15/80 (2013.01); G06N 10/00 (2019.01);
Abstract

Among the embodiments disclosed herein are example methods for generating all Clifford gates for a system of Majorana Tetron qubits (quasiparticle poisoning protected) given the ability to perform certain 4 Majorana zero mode measurements. Also disclosed herein are example designs for scalable quantum computing architectures that enable the methods for generating the Clifford gates, as well as other operations on the states of MZMs. These designs are configured in such a way as to allow the generation of all the Clifford gates with topological protection and non-Clifford gates (e.g. a π/8-phase gate) without topological protection, thereby producing a computationally universal gate set. Several possible realizations of these architectures are disclosed.


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