The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Jan. 09, 2017
Applicant:

Empire Technology Development Llc, Wilmington, DE (US);

Inventor:

Yan Solihin, Raleigh, NC (US);

Assignee:

EMPIRE TECHNOLOGY DEVELOPMENT LLC, Wilmington, DE (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 11/00 (2006.01); G11C 29/02 (2006.01); G11C 29/44 (2006.01); G11C 29/50 (2006.01); G11C 11/406 (2006.01); G11C 7/10 (2006.01); G11C 11/4074 (2006.01); G11C 29/00 (2006.01); G11C 11/40 (2006.01);
U.S. Cl.
CPC ...
G06F 11/004 (2013.01); G11C 7/1072 (2013.01); G11C 11/406 (2013.01); G11C 11/4074 (2013.01); G11C 11/40618 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G11C 29/44 (2013.01); G11C 29/50016 (2013.01); G11C 29/783 (2013.01); G11C 11/40 (2013.01); G11C 2211/4061 (2013.01);
Abstract

Techniques described herein generally include methods and systems related to designing and operating a DRAM device that has significantly reduced refresh energy use. A method for designing a DRAM optimizes or otherwise improves the DRAM for energy efficiency based on a measured or predicted failure probability of memory cells in the DRAM. The DRAM may be configured to operate at an increased refresh interval, thereby reducing DRAM refresh energy but causing a predictable portion of the memory cells in the DRAM to leak electrical energy too quickly to retain data. The DRAM is further configured with a selected number of spare memory cells for replacing the 'leaky' memory cells, so that operation of the DRAM at the increased refresh interval may result in little or no reduction in capacity of the DRAM.


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