The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Feb. 03, 2015
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Jack Hilaire Choquette, Palo Alto, CA (US);

Olivier Giroux, San Jose, CA (US);

Robert J. Stoll, Los Altos, CA (US);

Gary M. Tarolli, Concord, MA (US);

John Erik Lindholm, Saratoga, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); G06F 9/50 (2006.01); G06F 9/48 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/5038 (2013.01); G06F 9/3851 (2013.01); G06F 9/3887 (2013.01); G06F 9/4881 (2013.01);
Abstract

A streaming multiprocessor (SM) in a parallel processing subsystem schedules priority among a plurality of threads. The SM retrieves a priority descriptor associated with a thread group, and determines whether the thread group and a second thread group are both operating in the same phase. If so, then the method determines whether the priority descriptor of the thread group indicates a higher priority than the priority descriptor of the second thread group. If so, the SM skews the thread group relative to the second thread group such that the thread groups operate in different phases, otherwise the SM increases the priority of the thread group. f the thread groups are not operating in the same phase, then the SM increases the priority of the thread group. One advantage of the disclosed techniques is that thread groups execute with increased efficiency, resulting in improved processor performance.


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