The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Aug. 22, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Lakshminarayana B. Arimilli, Austin, TX (US);

Bartholomew Blaner, Underhill Center, VT (US);

William J. Starke, Round Rock, TX (US);

Randal C. Swanberg, Round Rock, TX (US);

Scott M. Willenborg, Stewartville, MN (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 12/0875 (2016.01); G06F 12/0811 (2016.01); G06F 12/0879 (2016.01); G06F 12/1081 (2016.01); G06F 12/0831 (2016.01);
U.S. Cl.
CPC ...
G06F 9/30032 (2013.01); G06F 9/30043 (2013.01); G06F 12/0811 (2013.01); G06F 12/0875 (2013.01); G06F 12/0879 (2013.01); G06F 12/1081 (2013.01); G06F 12/0831 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1048 (2013.01); G06F 2212/206 (2013.01); G06F 2212/452 (2013.01);
Abstract

A processor core of a data processing system, in response to a first instruction, generates a copy-type request specifying a source real address and transmits it to a lower level cache. In response to a second instruction, the processor core generates a paste-type request specifying a destination real address associated with a memory-mapped device and transmits it to the lower level cache. In response to the copy-type request, the lower level cache copies a data granule from a storage location specified by the source real address into a non-architected buffer. In response to the paste-type request, the lower level cache writes the data granule from the non-architected buffer to the memory-mapped device. In response to receipt of the data granule, the memory-mapped device stores the data granule in a queue in the system memory associated with a hardware device of the data processing system.


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