The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Oct. 29, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Sushma Devendrappa, San Jose, CA (US);

James Liu, Fremont, CA (US);

Changho Choi, Fremont, CA (US);

Sun Xiling, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/0616 (2013.01); G06F 3/0655 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 3/0688 (2013.01); G06F 12/0246 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1036 (2013.01); G06F 2212/7205 (2013.01); G06F 2212/7211 (2013.01);
Abstract

An electronic system includes: a key value storage device, configured to transfer user data, including: a non-volatile memory array, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to transfer the user data with the interface circuit or the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree to access the user data; and wherein: the interface circuit, connected to a device coupling structure, configured to receive the key value transfer command; and the device processor is configured to address the non-volatile memory array, the volatile memory, or both concurrently based on a key value transfer.


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