The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Oct. 13, 2015
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventor:

Hyunsic Choi, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); G02F 1/1333 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); G02F 1/1335 (2006.01); G02F 1/1343 (2006.01); G02F 1/1368 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136286 (2013.01); G02F 1/1362 (2013.01); G02F 1/1368 (2013.01); G02F 1/13439 (2013.01); G02F 1/133345 (2013.01); G02F 1/133514 (2013.01); G02F 1/136227 (2013.01); H01L 27/124 (2013.01); H01L 27/1222 (2013.01); H01L 27/1248 (2013.01); H01L 27/1262 (2013.01); H01L 29/66765 (2013.01); H01L 29/78669 (2013.01); G02F 2001/134372 (2013.01); G02F 2001/136218 (2013.01); G02F 2001/136295 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01);
Abstract

The present disclosure provides an array substrate, a method of manufacturing the same, a display panel and a display device. The array substrate comprises a plurality of gate lines and a plurality of data lines arranged to cross with each other and define a plurality of pixel areas, each of the pixel areas comprising a thin film transistor. The array substrate further comprises a first insulating layer arranged above the thin film transistors and the data lines; a metal layer arranged above the first insulating layer; a second insulating layer arranged above the metal layer; and a pixel electrode and a common electrode arranged above the second insulating layer, between which a third insulating layer is provided. The common electrode in each of the pixel areas at least comprises two slits and the metal layer overlies the data lines.


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