The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Feb. 03, 2016
Applicant:

Samsung Electro-mechanics Co., Ltd., Suwon-si, KR;

Inventors:

Seong Ryul Choi, Seoul, KR;

Suk Chang Hong, Yeongi-gun, KR;

Sang Kab Park, Cheongju, KR;

Kwang Seop Youm, Yeongi-gun, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H05K 1/18 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H05K 1/11 (2006.01); H01L 21/48 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 1/183 (2013.01); H01L 23/49811 (2013.01); H01L 23/5389 (2013.01); H05K 1/112 (2013.01); H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H05K 3/4697 (2013.01); H05K 2201/10492 (2013.01); H05K 2201/10515 (2013.01); H05K 2201/10734 (2013.01); Y10T 29/49165 (2015.01);
Abstract

Disclosed herein are a printed circuit board, a manufacturing method thereof, and a semiconductor package including the printed circuit board. The printed circuit board includes a base substrate including a plurality of circuit patterns, a cavity formed above the base substrate, a pad embedded in the base substrate and being exposed through the substrate bottom surface of the cavity, and an electronic component mounted in the cavity and electrically connected to the pad. According to the present invention, a cavity having a predetermined depth is formed in a base substrate of a printed circuit board so as to mount an electronic component therein, such that a gap between an upper semiconductor package and a lower semiconductor package may be obtained even if pitches between the balls are decreased for high density and high performance of the upper semiconductor package in the manufacturing of a semiconductor package having a PoP structure.


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