The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Sep. 13, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

David Symons, Oxon, GB;

Paul Hanham, Wiltshire, GB;

Francesco Giorgio, Oxon, GB;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1125 (2013.01); G06F 3/065 (2013.01); G06F 3/0619 (2013.01); G06F 3/0688 (2013.01);
Abstract

A method of providing, by a controller, a log likelihood ratio (LLR) to a low-density parity check (LDPC) decoder, the method comprising storing, in a non-volatile memory controller, a look-up table for storing LLR values of at least one bit representing a charge state of a cell of the plurality of cells in the memory. The controller determines a cell charge state of the target cell, calculates a value representative of the difference in charge states of the target cell and at least one of a plurality of neighboring cells. The controller compares the calculated value with at least one predetermined threshold value, and sets at least one address bit of an address to the look-up table if the calculated value exceeds the at least one threshold value. The controller extracts a new LLR value from the look-up table, and provides the new LLR value to the LDPC decoder.


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