Techniques for power efficient oversampling successive approximation register

Abstract

Systems and methods are disclosed for a noise-shaping successive approximation register (SAR) analog-to-digital-converter (ADC) using Sampled Analog Technology (SAT) filter techniques for filter construction. A SAR ADC includes an SAR for receiving an analog input signal and outputting a digital decision, a digital-to-analog converter and logic circuitry for converting the digital decision of the SAR to a present analog residue for a present conversion cycle, a filter for processing a previous analog residue from a previous conversion cycle, and for feeding a processed previous analog residue back to the SAR, a summer for summing the processed previous analog residue from the filter and the present analog residue, and generating a summer output, and a comparator for comparing the summer output and a first reference signal and generating a comparator output. The filter includes a capacitor array for filtering the previous analog residue to generate the processed previous analog residue.