The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Jun. 28, 2016
Applicant:

Altera Corporation, San Jose, CA (US);

Inventor:

Yanjing Ke, Union City, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 5/15 (2006.01); H03K 5/156 (2006.01); H03K 19/20 (2006.01); H03M 9/00 (2006.01); H03K 19/173 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
H03K 5/15066 (2013.01); H03K 5/1565 (2013.01); H03K 19/1737 (2013.01); H03K 19/17744 (2013.01); H03K 19/20 (2013.01); H03M 9/00 (2013.01);
Abstract

One embodiment relates to a multiple-channel serializer circuit that includes a plurality of one-channel serializers. A one-channel serializer of the plurality of one-channel serializes includes a local 2× frequency clock generator with a non-divider structure. Other embodiments relate to methods of using a non-divider circuit to generate a local 2× frequency clock signal in a one-channel serializer of a multiple-channel serializer. Another embodiment relates to a local 2× frequency clock generator circuit with a non-divider structure. The local 2× frequency clock generator circuit includes a first circuit path which is selected by multiplexers for a first serialization ratio and may also include a second circuit path which is selected by the multiplexers for a second serialization ratio. Other embodiments and features are also disclosed.


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