The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Mar. 23, 2018
Applicant:

3-5 Power Electronics Gmbh, Dresden, DE;

Inventor:

Volker Dudek, Ettlingen, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/861 (2006.01); H01L 29/20 (2006.01); H01L 29/36 (2006.01); H01L 29/32 (2006.01); H01L 29/872 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/8613 (2013.01); H01L 29/20 (2013.01); H01L 29/32 (2013.01); H01L 29/36 (2013.01); H01L 29/861 (2013.01); H01L 29/66204 (2013.01); H01L 29/872 (2013.01);
Abstract

A stacked III-V semiconductor diode having an n-layer with a dopant concentration of at least 10N/cm, an n-layer with a dopant concentration of 10-10N/cm, a layer thickness of 10-300 microns, a p-layer with a dopant concentration of 5×10-5×10cm, with a layer thickness greater than 2 microns, wherein said layers follow one another in the sequence mentioned, each comprising a GaAs compound. The n-layer or the p-layer is formed as the substrate and a lower side of the n-layer is materially bonded with an upper side of the n-layer, and a doped intermediate layer is arranged between the n−-layer and the p+-layer and materially bonded with an upper side and a lower side.


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