The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Feb. 12, 2008
Applicants:

Masahiko Hata, Tsuchiura, JP;

Hiroyuki Sazawa, Tsukuba, JP;

Naohiro Nishikawa, Ichihara, JP;

Inventors:

Masahiko Hata, Tsuchiura, JP;

Hiroyuki Sazawa, Tsukuba, JP;

Naohiro Nishikawa, Ichihara, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 31/00 (2006.01); H01L 29/778 (2006.01); H01L 29/207 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7783 (2013.01); H01L 29/207 (2013.01); H01L 29/66462 (2013.01); H01L 21/0242 (2013.01); H01L 21/0254 (2013.01); H01L 21/0262 (2013.01); H01L 21/02458 (2013.01); H01L 21/02502 (2013.01); H01L 21/02581 (2013.01); H01L 29/2003 (2013.01);
Abstract

The present invention provides an epitaxial substrate for field effect transistor. In the epitaxial substrate for field effect transistor, a nitride-based Group III-V semiconductor epitaxial crystal containing Ga is interposed between the ground layer and the operating layer, and the nitride-based Group III-V semiconductor epitaxial crystal includes the following (i), (ii) and (iii). (i) a first buffer layer containing Ga or Al and containing a high resistivity crystal layer having added thereto compensation impurity element present in the same period as Ga in the periodic table and having small atomic number; (ii) a second buffer layer containing Ga or Al, laminated on the operating layer side of the first buffer layer; and (iii) a high purity epitaxial crystal layer containing acceptor impurities in a slight amount such that non-addition or depletion state can be maintained, provided between the high resistivity layer and the operating layer.


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