The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2019
Filed:
Dec. 14, 2017
Applicant:
Mediatek Inc., Hsin-Chu, TW;
Inventors:
Chih-Chun Hsu, New Taipei, TW;
Sheng-Mou Lin, Hsinchu, TW;
Assignee:
MEDIATEK INC., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/08 (2006.01); H01L 23/66 (2006.01); H01L 23/31 (2006.01); H01L 23/552 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 23/3128 (2013.01); H01L 23/552 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/1421 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/3025 (2013.01);
Abstract
A semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region, a semiconductor die disposed on the package substrate in the first region, a conductive shielding element disposed on the package substrate and covering the semiconductor die, and a three-dimensional (3D) antenna. The 3D antenna includes a planar structure portion disposed on the package substrate in the second region, and a bridge structure portion above the planar structure portion and connected thereto.