The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Jan. 08, 2018
Applicant:

AU Optronics Corporation, Hsin-chu, TW;

Inventors:

Chuang-Cheng Yang, Hsin-chu, TW;

Chun-Feng Lin, Hsin-chu, TW;

Ming-Hsien Lee, Hsin-chu, TW;

Kai-Wei Hong, Hsin-chu, TW;

Chun-Da Tu, Hsin-chu, TW;

Yi-Cheng Lin, Hsin-chu, TW;

Assignee:

AU OPTRONICS CORPORATION, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/2092 (2013.01); G09G 3/3677 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/08 (2013.01);
Abstract

Provided is a gate driving circuit, coupled to a pixel array having multiple gate lines. The gate driving circuit includes multiple shift registers and multiple pull-up transistor, coupled to the pixel array and separately located on two opposite sides of the pixel array. Shift registers located on a same side are sequentially coupled to each other. An n(n is a positive integer) pull-up transistor includes: a control end, coupled to a control end of a driving transistor of an (n−1)shift register located on a same side as the npull-up transistor; a first end, used to receive a clock signal, where the clock signal is further input to an nshift register of the shift registers located on an opposite side of the npull-up transistor; and a second end, coupled to an ngate line of the pixel array and used to drive the ngate line.


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