Methods for incremental circuit design legalization during physical synthesis

Abstract

Configuration data for an integrated circuit may be generated using logic design equipment to implement a logic design on the integrated circuit. The equipment may perform incremental physical synthesis, timing optimization, and legalization operations on the logic design. The equipment may identify timing and legalization constraints and logic blocks that fail the timing constraints, and may determine whether modifying and/or moving the blocks to new locations satisfy the legalization constraints while improving the timing of the design. If the legalization constraints are not satisfied, the design equipment may recursively move non-critical logic blocks to new locations while ensuring that the legalization and timing constraints are satisfied for each move such that the timing of the design is improved. This may be repeated in multiple rounds of adjustment. A netlist may be generated after the moves are performed. The configuration data may be generated based on the netlist.