The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2019
Filed:
Feb. 06, 2018
Zipalog, Inc., Plano, TX (US);
Felicia James, Carrollton, TX (US);
Michael Krasnicki, Richardson, TX (US);
ZIPALOG, INC., Plano, TX (US);
Abstract
A computer implemented method of passive verification of an electronic design, comprising receiving an electronic design file of said electronic design comprised at least in part of a mixed signal or analog system including a plurality of subsystems. At least one analog subsystem of the plurality of subsystems has at least two design representations within the electronic design file that are intended to be equivalent for the at least one analog subsystem being simulated. First and second input subsystem data is collected for a first and second subsystem design representation of the at least two design representations from an analog stimulus to at least one input of the first and second subsystem design representation which is analog. First and second output subsystem data is collected from at least one output of the first and second subsystem design representation of the at least two design representations caused by the analog stimulus to the at least one input of the first and second subsystem design representation. At least one parameter of said first and second input subsystem data is analyzed with respect to said first and second output subsystem data. The at least one parameter of the first subsystem design representation is compared with the at least one parameter of second subsystem design representation. The electronic design file of the electronic design is verified responsive to the determined analysis between the at least one input of the subsystem and the at least one output of the subsystem for each of the first and the second subsystem design representations.