The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Jun. 28, 2018
Applicant:

Eta Compute, Inc., Westlake Village, CA (US);

Inventors:

Ben Melton, Thousand Oaks, CA (US);

Bryan Garnett Cope, Austin, TX (US);

Assignee:

Eta Compute, Inc., Westlake Village, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); H03K 19/20 (2006.01); G06F 17/50 (2006.01); G06F 1/3203 (2019.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3871 (2013.01); G06F 1/3203 (2013.01); G06F 17/5059 (2013.01); H03K 19/0008 (2013.01); H03K 19/20 (2013.01);
Abstract

There is disclosed a self-timed processor. The self-timed processor includes combinatorial logic comprising multi-rail delay insensitive asynchronous logic (DIAL) to output one or more multi-rail data values to a multiplexer. It also includes a test pattern input to output a test pattern bit stream of multi-rail test data values to the multiplexer. The multiplexer has Boolean logic to output one or more multi-rail multiplexed values to a latch. The multiplexer also has a single rail selector input to select whether the multi-rail multiplexed values are the multi-rail data values or the multi-rail test data values.


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