The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Nov. 09, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kyu-Hyoun Kim, Chappaqua, NY (US);

Kevin Mcilvain, Delmar, NY (US);

Adam J. McPadden, Underhill, VT (US);

Nandita A. Mitra, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 16/04 (2006.01); G06F 11/07 (2006.01); G11C 29/02 (2006.01); G11C 16/10 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0604 (2013.01); G06F 3/0653 (2013.01); G06F 11/073 (2013.01); G11C 7/1087 (2013.01); G11C 16/04 (2013.01); G11C 29/022 (2013.01); G11C 29/028 (2013.01); G11C 7/1039 (2013.01); G11C 16/102 (2013.01); G11C 2029/0409 (2013.01); H01L 2924/1423 (2013.01);
Abstract

A nonvolatile queue manager queues entries of host data from one or more host channels to one or more write buffers for storage in one or more nonvolatile memory devices of a nonvolatile memory array. The nonvolatile queue manager compares a number of the entries queued to one or more nonvolatile memory holdup power write thresholds based on detecting a power loss event. The nonvolatile queue manager tracks one or more locations in the nonvolatile memory array targeted by one or more of the entries extending beyond the one or more nonvolatile memory holdup power write thresholds. The nonvolatile queue manager initiates a mitigation action on a subsequent restoration of power to handle the one or more locations in the nonvolatile memory array targeted by one or more of the entries extending beyond the one or more nonvolatile memory holdup power write thresholds.


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